1. Field of the Invention
The present invention relates to a frequency synthesizer used for a high-frequency multi-channel radio communication apparatus or the like, and more particularly to a phase-locked loop (PLL) type frequency synthesizer characterized by the speedy frequency switching operation.
2. Description of the Prior Art
The frequency synthesizer is not only an important component of the multi-channel communication apparatus but is also used widely in various radio communication apparatus. Recent radio communication system is changing from analogue to digital. As the time-division multiple access (TDMA) has been adopted in such digital radio communication system, the speed-up of the inter-channel frequency switching operation is becoming very important for the frequency synthesizer.
Hereinafter, a conventional frequency synthesizer will be described.
FIG. 8 shows a circuit configuration of one example of the conventional frequency synthesizer. In FIG. 8, a reference numeral 101 represents a voltage-controlled oscillator, and a reference numeral 102 represents a high-frequency output terminal. A reference numeral 103 represents a first frequency divider which divides the output frequency of the voltage-controlled oscillator 101, and a reference numeral 104 represents a basic oscillator (e.g. a normal temperature-compensated crystal oscillator). A reference numeral 105 represents a second frequency divider which divides the output frequency of the basic oscillator 104, and a reference numeral 106 represents a phase detector (e.g. a normal digital phase/frequency comparator) which detects the phase difference between the output of the first frequency divider 103 and the output of the second frequency divider 105.
A reference numeral 107 represents a charge pump which transforms the output of the phase detector 106 into a drive signal for an integrator, and a reference numeral 108 represents a loop filter serving as the integrator, which feeds the output of the charge pump 107 back to the voltage-controlled oscillator 101 after removing high-frequency components thereof. And, a reference numeral 109 represents a phase-locked loop circuit which is constituted by above components 101 through 108.
An operation of thus constituted frequency synthesizer will be discussed below.
In the phase-locked condition, the first and second frequency dividers generate individual outputs identical with each other in their frequencies (reference frequencies) and phases. Therefore, the charge pump generates a high-impedance output.
On the other hand, output frequencies of these first and second frequency dividers become out of phase with each other when the channel is changed. In this case, the phase detector executes the frequency correction by which the frequency is pulled in so as to approximate to the target frequency, and then charges or discharges the loop filter through the charge pump. (Frequency pull-in mode)
Furthermore, the phase detector executes the phase correction so as to pull in the frequency to be identical with the target frequency, and charges or discharges the loop filter through the charge pump. (Phase pull-in mode)
A series of above operations becomes speedy with high loop gain; i.e. high sensitivity of the voltage-controlled oscillator, small frequency dividing number (i.e. high reference frequency), or small time constant of the loop filter.
However, the reference frequency cannot be set freely in the multi-channel radio communication apparatus as it is univocally determined in accordance with channel spacing. If the sensitivity of the voltage-controlled oscillator is increased, the S/N (signal/noise) or C/N (carrier/noise) ratio of the voltage-controlled oscillator itself is deteriorated. If the time constant of the loop filter is decreased, the noise bandwidth is increased. Therefore, there was a problem such that the S/N or C/N ratio of the frequency synthesizer is deteriorated.